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EM MICROELECTRONIC-MARIN SA
H6060
Self Recovering Watchdog
Features
Self recovering watchdog function: reset goes active after the 1st timeout period, reset goes inactive again after the 2nd timeout period, repeated active reset signal until the system recovers Standard timeout period and power-on reset time (100 ms), externally programmable if required Unregulated DC monitoring (VIN) with 3 standard or programmable trigger voltages for: power-on reset initialization, advanced power-fail warning (SAVE), reset at power-down (RES) Regulated DC monitoring (VDD): power-on reset initialization enabled only if VDD 3.5 V Internal voltage reference Works down to 1.6 V supply voltage Push-pull or Open drain outputs Low current consumption Available for normal and extended temperature ranges DIP8 and SO8 package
Typical Operating Configuration
Voltage Regulator
5V
VIN TCL VSS H6060
VDD RES SAVE RES
NMI MicroRES processor I/O GND
Description
The H6060 is a monolithic low-power CMOS device combining a programmable timer and a series of voltage comparators on the same chip. The device is specially suited for watchdog functions such as microprocessor and supply voltage monitoring. If the P system malfunctions, the watchdog will recover it by issuing repeated active reset signals. The voltage monitoring part provides double security by combining both the unregulated voltage (VIN) and the regulated voltage (VDD) monitoring simultaneously. The H6060 initializes the power-on reset after VIN reaches VSH (see table 4) and VDD rises above 3.V. If VIN drops below VSL (see table 4), the H6060 gives an advanced warning signal for register saving and if the voltage drops further below VRL (see table 4), RES and RES go active. The H6060 functions at any supply voltage down to 1.6 V and is therefore particularly suited for start-up and shut-down control of microprocessor systems. Fig. 1
Pin Assignment
DIP8 / SO8
VIN TCL RC VSS H6060
VDD RES SAVE RES
Applications
Microprocessor and microcontroller systems Point of sales equipment Telecom products Automotive subsystems
Fig. 2
1
H6060
Absolute Maximum Ratings
Parameter Voltage VDD to VSS Voltage at any pin to VSS Voltage at any pin to VDD (except VIN) Voltage at VIN to VSS Current at any output Storage temperature Symbol VDD VMIN VMAX VINMAX IMAX TSTO Conditions - 0.3 to + 8 V - 0.3 + 0.3 + 15 V 10 mA -65...+150 C Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level.
Operating Conditions
Parameter Symbol Min. Typ Max. Units -40 1.6 0 0 +85 5.5 VDD 12 1 C V V V F k Table 2 Operating temperature TAI Industrial Supply voltage VDD Comparator input voltage Version 13, 14, 15, 16 VIN Version 11,12 VIN RC-oscillator programming (see Fig. 15) External capacitance C1 R1 External resistance
Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static
10
Leakage < 1 A
Electrical Characteristics
Parameter VDD activation threshold VDD deactivation threshold Supply current Input VIN, TCL Leakage current Input current on pin VIN TCL input low level TCL input high level SAVE , RES , RES outputs Leakage currents Drive currents (all versions) Drive currents (versions 12, 14,16)1)
1)
VDD = 5.0 V, TA = -40 to +85 C, unless otherwise specified
Symbol VON VOFF IDD IIP IIN VIL VIH IOLK IOL IOL IOL IOH IOH IOH
Test Conditions TA = 25 C TA = 25 C RC open, TCL at VDD or VSS VSS VIP VDD; TA = 85 C Versions 11, 12; VIN = 10 V
Min. 3
Typ. VON - 0.3 80 0.005 100
Max. 3.5 140 1 180 0.8
Units V
V A
A A
2.4 Versions 11, 13, 15; VOUT = VDD VOL = 0.4 V VDD = 3.5 V; VOL = 0.4 V VDD = 1.6 V; VOL = 0.4 V VOH = 4.0 V VDD = 3.5 V; VOH = 2.8 V VDD = 1.6 V; VOH = 1.2 V 0.05 8 8
V V
1
A
3.2 2 80 3.2 2 80
mA mA
A
mA mA
A
Versions: 11, 13, 15 = open drain outputs; 12, 14, 16 = push-pull outputs
Table 3
Voltage thresholds at TA = 25 C
VIN Surveillance Version 1) 11, 12 13, 14 15, 16
Comparator Reference VDD VDD Band-gap reference
Input Resistance on VIN (RVIN) 100k 100M 100M
VSH 9.00 2.25 2.00
Threshold VSL VRL 8.00 2.00 1.95 7.00 2) 1.75 2) 1.90
Thresholds
Tolerance
Ratio
Tolerance
3)
5% 5% 10%
2% 2% 2% Table 4
1) 2)
Versions: 11, 13, 15 = open drain ouputs; 12, 14, 16 = push-pull outputs at VDD = 5 V 3) Threshold ratio tolerance is defined as the tolerance of VSH / VSL and VSL / VRL.
2
H6060
Timing Characteristics
VDD = 5.0 V, TA = -40 C to +85 C, unless otherwise specified
Parameter Propagation delays TCL to output pins VIN to output pins Logic transition times on all output pins Timeout period TTCL input pulse width Power-on reset debounce VIN low pulse
Symbol TDIDO TAIDO TTR TTO TTO TTCL TDB TVINL
Test Conditions
Min.
Typ. 250 4 30
Max. 500 10 100 160 200
Units ns s ns ms ms ns ms s Table 5
Excluding debounce time TDB Load 10 k, 100 pF RC open, unshielded, TA = 25 C RC open, unshielded (not tested) 60 45 150
100
TTO/64 Where debounce time TDB Is guaranteed 10
Timing Waveforms
Voltage Reaction: VDD Monitoring
VDD VON VOFF
VIN monitoring enabled Fig. 3 Voltage Reaction: VIN Monitoring VIN VSH VSL VRL TVINL Conditions: VDD > VON. No timeout.
TTO 0 SAVE RES RES
Timer Start Power-on Reset
TTO TDB
TDB
Timer Stop Timer Start
Power-on Reset
No Power-on Reset (as VIN > VRL)
Fig. 4 3
H6060
Timer Reaction TTCL Conditions: VIN > VRL after power-up sequence TTO TTO TTO TCL RES
TTO
RES
Timer Reset Timeout Timer Reset Timer Reset
Fig. 5
Combined Voltage and Timer Reaction VIN VSH VSL VRL TDB SAVE RES RES TCL
Initialisation
TTO
TTO
TTO
RES
RES
Timeout Recover
Timer Reset
Timer Stop
Fig. 6
Block Diagram
VDD
1 2
VIN
Band-Gap Reference
VSH
+ +
Save Control
SAVE
VSL
+
VRL
Reset Control
RES RES
+ 3
VSS RC
Version Connections 11, 12 1 and 3 13, 14 1 15, 16 2
OSC
Timer
TCL 4
Fig. 7
H6060
Pin Description
Pin Name 1 2 3 4 5 6 7 8 VIN TCL RC VSS RES SAVE RES VDD Function Voltage sense input Timer clear input signal RC oscillator tuning input GND terminal Active low reset output Save output Active high reset output Positive supply voltage terminal Table 6 Version 11, 12: have an internal voltage divider for direct monitoring of the unregulated voltage without external components. Voltage Regulator 5V VDD RES SAVE RES
VSS
Functional Description
Supply Lines The circuit is powered through the VDD and VSS pins. It monitors both its own VDD supply and a voltage applied to the VIN input. VDD Monitoring During power-up the VIN monitoring is disabled and RES, RES and SAVE stay active low as long as VDD is below VON (3.5 V). As soon as VDD reaches the VON level, the state of the outputs depend on the watchdog timer and the voltage at VIN relative to the thresholds (see Fig. 4). If the supply voltage VDD falls back below VOFF (VON - 0.3 V) the watchdog timer and the VIN monitoring are disabled and the outputs RES, RES and SAVE become active. The VDD line should be free of voltage spikes. VIN Monitoring The analog voltage comparators compare the voltage applied to VIN (typically connected to the input of the voltage regulator) with the stabilized supply voltage VDD (versions 11, 12, 13, 14) or with the bandgap voltage (versions 15, 16) (see Fig. 7). At power-up, when VDD reached VON and VIN reaches the VSH level, the SAVE output goes inactive, and the timer starts running, setting RES and RES in active after the time TTO (see. Fig. 4). If VIN falls below VSL , the SAVE output goes active and stays active until VIN rises again above VSH . If VIN falls below the voltage VRL , RES and RES will become active and the on-chip timer will stop. When VIN rises again above VSH, the timer will initiate a power-up sequence. The RES and RES outputs may however be influenced independently of the voltage VIN by the timer action, see section Combined Voltage and Timer Action". Monitoring the rough DC side of the regulator, as shown in Fig. 12, is the only way to have advanced warning of power-down. Spikes on VIN should be filtered if they are likely to exceed the value (VSL - VRL ). The combination of VIN and VDD monitoring provide high system security: if VIN rises much faster than VDD , then the device starts the power-on sequence only when VDD reached VON (Fig. 11). Short circuits on the regulated supply voltage can be detected. Voltage Thresholds on VIN The H6060 is available with 3 different sets of thresholds: Note: internal threshold levels: 9/8/7 V at VDD = 5 V (thresholds relative to VDD, see table 4 and Fig. 8 fig. 4) RVIN = ~100 k Version 13, 14: monitor the unregulated voltage and are ideal for programming of the VIN voltage thresholds. Fixed resistor values can be used for programming. any voltage Voltage Regulator VIN 5V
H6060 11, 12 H6060 13, 14
VIN
VDD RES SAVE RES
VSS
Note: internal threshold levels: 2.25/2.00/1.75 V at VDD = 5 V (thresholds relative to VDD, see Fig. 9 table 4 and fig. 4) RVIN = ~100 M Version 15, 16: monitor the regulated voltage. They are suited to applications where the unregulated voltage is not available. (The tolerance is 10%, see table 4. For tighter tolerances, trimming can be used, see fig. 10).
H6060 15, 16
VIN
VDD RES SAVE RES
VSS
Note: internal threshold levels: 2.00/1.95/1.90 V (thresholds relative to internal bandgap reference) RVIN = ~100 M Fig. 10 5
H6060
Monitoring of the unregulated voltage requires versions 11, 12, 13 and 14. These versions are based on the principle that VDD rises with VIN on power-up an VDD holds up for a certain time after VIN starts dropping on powerdown. The versions 11 and 12 have a 100 k nominal resistance from VIN to VSS (internal voltage divider). The versions 13, 14, 15 and 16 have high impedance VIN inputs (see fig. 7 and table 4) for external threshold voltage programming by a voltage divider on pin VIN. The levels obtained are proportional to the internal levels VSH, VSL and VRL on the chip itself (see Electrical Specifications). Timer Programming With pin RC unconnected, the on-chip RC oscillator together with its divider chain give a timeout TTO of typically 100 ms. To program different TTO, an approximation for calculating component values is given by the formula: (32 + C1 ) 2 TTO = 0.75 + 8. 192 V -1 5.5 + DD R1 R1 min. = 10 k, C1 max. = 1 F If R1 is in M and C1 in pF, TTO will be in ms. A resistor decreases and a capacitor increases the interval to timeout. Excellent temperature stability of TTO can be achieved by using external components. A precise square wave of period 2 x TTO is generated at the outputs RES and RES when TCL is tied to either VDD or VSS. The oscillator and watchdog timer start running when both VIN is greater than VSH (see fig. 6) and VDD is greater than VON (see fig. 3). They will remain running while both VIN is greater than VRL and VDD is greater than VOFF (see fig. 3). Timer Clearing and RES/RES Action A negative edge or a negative pulse at the TCL input for longer than 150 ns will reset the timer and set RES and RES inactive. If a further TCL signal edge or pulse is applied before TTO timeout, RES and RES will remain inactive and the timer will again be reset to zero (see fig. 5). If no TCL signal is applied before the TTO timeout, RES and RES will start to generate square waves of period 2 x TTO starting with the inactive state. The watchdog will remain in this state until the next TCL signal appears, or until a fresh power-up sequence. Combined Voltage and Timer Action The combination of voltage and timer actions is illustrated by the sequence of events shown in fig. 6. One timeout period after VIN reaches VSH, during powerup, RES and RES go inactive. A TCL pulse will have no effect until this power-on reset delay is completed. After completing the power-up sequence the watchdog timer starts acting. If no TCL pulse occurs, RES and RES go active after one timeout period TTO. After each subsequent timeout period, without a timer clear pulse at TCL, RES and RES change polarity providing square wave signals. A TCL pulse clears the watchdog timer and causes RES and RES to go inactive. A voltage drop below the VRL level overrides the timer and immediately forces RES, RES and SAVE active. Any further TCL pulse has no effect until the next power-up sequence is completed.
Typical Applications
Microprocessor Watchdog with Power-On Reset and Voltage Monitor
Unregulated Voltage R1 =470 k
Voltage Regulator
5 V Regulated Voltage
H6060
Address SEL Decoder Latched Address Bus C1 = 220 pF RD RESET Microprocessor IRQ
VIN TCL RC VSS
VDD RES SAVE RES
RAM CS CS
TTO = ~300 ms 6
Fig. 11
H6060
Voltage Monitor with Spike Suppression 1) R/F shields for noisy environments. 5 VDC 1) 1) 1) VIN RC VSS H6060 11 VDD 2.7 k +12 VDC rough Voltage Regulator
Z-15
330 nF
SAVE RES
TCL
Fig. 12
Watchdog and Power-On Reset
TCL VSS
H6060 13 to 16
VIN
VDD RES RES
If precise thresholds are not required then VIN monitoring on versions 13 to 16 can be disabled by tying VIN to VDD. The VDD monitoring is still active and power-up reset occurs at VON and power-down reset at VOFF threshold.
Fig. 13 External Programming of RC Oscillator
VDD H6060 TCL RC C1 VSS RES RES
R1 H6060 TCL RC VSS
VDD RES RES
R1 H6060 TCL RC C1 VSS
VDD
RES
RES
C1 increases TTO
R1 shortens TTO
This circuit provides independent programming of both timeout period
and power-on reset delay.
Note: if external components R1 and C1 are used, a tighter timeout period tolerance can be achieved.
Fig. 14 7
H6060
Package Information
Dimensions of 8-Pin SOIC Package
D C
E 0 - 8 L H Dimensions in mm Min Nom Max A 1.35 1.63 1.75 A1 0.10 0.15 0.25 B 0.33 0.41 0.51 C 0.19 0.20 0.25 D 4.80 4.93 5.00 E 3.80 3.94 4.00 e 1.27 H 5.80 5.99 6.20 L 0.40 0.64 1.27 Fig. 15
A1 B
A
e
4
3
2
5
6
7
8
Dimensions of 8-Pin Plastic DIP Package
A1
A2
A C
L b3 b2 b Dimensions in mm e eA eB
4
3
2
1 E1 E
5
6
7
8
A A1 A2 b b2 b3 C
Min. Nom. Max. 5.33 0.38 2.92 3.30 4.95 0.35 0.45 0.56 1.14 1.52 1.78 0.76 0.99 1.14 0.20 0.25 0.35
D E E1 e eA eB L
Min. Nom. Max. 9.01 9.27 10.16 7.62 7.87 8.25 6.09 6.35 7.11 2.54 7.62 10.92 2.92 3.30 3.81 Fig. 16
8
H6060
Ordering Information
When ordering please specify complete part number.
Part Number H6060V11SO8A * H6060V11SO8B * H6060V11DL8A * H6060V13SO8A * H6060V13SO8B * H6060V13DL8A * H6060V15SO8A H6060V15SO8B H6060V15DL8A H6060V12SO8A * H6060V12SO8B * H6060V12DL8A * H6060V14SO8A H6060V14SO8B H6060V14DL8A H6060V16SO8A H6060V16SO8B V14 2.00 Push-pull V12 8.00 V15 1.95 V13 2.00 Open drain V11 8.00 Version Threshold (see Table 4) Output Package 8-pin SOIC 8-pin SOIC 8-pin plastic DIP 8-pin SOIC 8-pin SOIC 8-pin plastic DIP 8-pin SOIC 8-pin SOIC 8-pin plastic DIP 8-pin SOIC 8-pin SOIC 8-pin plastic DIP 8-pin SOIC 8-pin SOIC 8-pin plastic DIP 8-pin SOIC Delivery Form Stick Tape&Reel Stick Stick Tape&Reel Stick Stick Tape&Reel Stick Stick Tape&Reel Stick Stick Tape&Reel Stick Stick Package Marking Temperature (first line) 606011 606011 H606011 606013 606013 H606013 606015 606015 H606015 606012 606012 H606012 606014 606014 H606014 606016 -40C to +85C
606016 V16 1.95 8-pin SOIC Tape&Reel H606016 H6060V16DL8A 8-pin plastic DIP Stick * = non stock items. Might be available on request and upon minimum order quantity (please contact EM Microelectronic)
EM Microelectronic-Marin SA cannot assume any responsibility for use of any circuitry described other than entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
(c) 2002 EM-Microelectronic-Marin SA, 03/02, Rev. H/457
9 EM Microelectronic-Marin SA, CH - 2074 Marin, Switzerland, Tel. +41 - (0)32 75 55 111, Fax +41 - (0)32 75 55 403

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